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1 of 14 022108 features ? temperature measurements require no external components ? measures temperatures from -55c to +125c (-67f to +257f) ? 2c accuracy over a -25c to +100c range ? thermometer resolution is user- configurable from nine (default) to 12 bits (0.5 c to 0.0625 c resolution) ? 9-bit conversion time is 150ms (max) ? thermostatic settings are user-definable ? data is read/written via 2-wire serial (interface (sda and scl pins) ? multidrop capability simplifies distributed temperature-sensing applications ? wide power-supply range (+2.7v to +5.5v). ? pin/software compatible with the lm75 ? available in 8-pin max ? and so packages. see table 1 for ordering information ? applications include personal computers, cellular base stations, office equipment, or any thermally sensitive system pin assignment pin description sda ? open-drain data i/o scl ? clock input gnd ? ground o.s. ? open-drain thermostat output a 0 ? address input a 1 ? address input a 2 ? address input v dd ? power supply description the ds75 digital thermometer and th ermostat provides 9, 10, 11, or 12 -bit digital temperature readings over a -55c to +125c range with 2c accuracy over a -25c to +100c range. at power-up, the ds75 defaults to 9-bit resolution for software compatibility with the lm75. communi cation with the ds75 is achieved via a simple 2?wire serial interface. three address pi ns allow up to eight ds75 devices to operate on the same 2?wire bus, which greatly simp lifies distributed temperatur e sensing applications. the ds75 thermostat has a dedicated open?drain output (o.s.) and programmable fault tolerance, which allows the user to define the num ber of consecutive error conditions that must occur before o.s is activated. there are two thermostatic operating m odes that control thermost at operation based on user- defined trip-points (t os and t hyst ). a block diagram of the ds75 is shown in figure 1 and detailed pin descriptions are given in table 2. ds75 digital thermometer and thermostat www.maxim-ic.com ds75u+ ( sc l v dd a 0 a 1 a 2 gnd o.s. s d a 6 8 7 5 3 1 2 4 ds75 DS75S+ (8-pin so ? 150mil) sc l v dd a 0 a 1 a 2 gnd o.s. s d a 6 8 7 5 3 1 2 4 ds75 max is a registered trademark of maxim integrated products, inc.
ds75 2 of 14 table 1. ordering information ordering number package marking description DS75S+ ds75 (see note) ds75 in lead-free 150mil 8-pin so DS75S+t&r ds75 (see note) ds75 in lead-free 150mil 8-pin so, 2500-piece tape-and-reel ds75u+ ds75 (see note) ds75 in lead-free 8-pin max ds75u+t&r ds75 (see note) ds75 in lead-free 8-pin max, 3000-piece tape-and-reel DS75S ds75 ds75 in 150mil 8-pin so DS75S/t&r ds75 ds75 in 150mil 8-pin so, 2500-piece tape-and-reel ds75u ds75 ds75 in 8-pin max ds75u/t&r ds75 ds75 in 8-pin max, 3000-piece tape-and-reel note: a "+" symbol will also be marked on the package near the pin 1 indicator table 2. detailed pin description pin symbol description 1 sda data input/output pin for 2-wire serial communi cation port. open drain. 2 scl clock input pin for 2-wire serial communication port. 3 o.s. thermostat output . open drain. 4 gnd ground pin. 5 a 2 address input pin. 6 a 1 address input pin. 7 a 0 address input pin. 8 v dd supply voltage. +2.7v to +5.5v supply pin.
ds75 3 of 14 figure 1. ds75 functional block diagram t os and t hyst re g i s ter s configuration re g i s ter temperature re g i s ter oversampling m o d u lat o r precision referen c e digital de c imat o r address and i/o control a 1 a 2 a 0 scl sd a v dd gnd thermostat co mparat o r r p o.s.
ds75 4 of 14 absolute maxi mum ratings* voltage on v dd , relative to ground ?0.3v to +7.0v voltage on any other pin, re lative to ground ?0.3v to (v dd + 0.3v) operating temperature ?55 c to +125 c storage temperature ?55 c to +125 c soldering temperature +260 c for 10 seconds * these are stress ratings only and f unctional operation of the device at these or any other conditions above those indicated in the operation sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (-55c to +125c; 2.7v v dd 5.5v) parameter symbol condition min max units notes supply voltage v dd 2.7 5.5 v -25 to +100 2.0 thermometer error t err -55 to +125 3.0 c 2 input logic high v ih 0.7v dd v dd +0.5 v 1 input logic low v il -0.5 0.3v dd v 1 v ol1 3 ma sink current 0 0.4 sda output logic low voltage v ol2 6 ma sink current 0 0.6 v 1 o.s. saturation voltage v ol 4 ma sink current 0.8 v 1, 2 input current each i/o pin 0.4 < v i/o < 0.9 v dd -10 +10 a i/o capacitance c i/o 10 pf standby current i dd1 1 a 3, 4 active temp. conversions 1000 active current i dd communica- tion only 100 a 3, 4
ds75 5 of 14 ac electrical characteristics (-55c to +125c; 2.7v v dd 5.5v) parameter symbol condition min typ max units notes resolution 9 12 bits 9-bit conversions 150 10-bit conversions 300 11-bit conversions 600 temperature conversion time t convt 12-bit conversions 1200 ms scl frequency f scl 400 khz bus free time between a stop and start condition t buf 1.3 s 5 start and repeated start hold time from falling scl t hd:sta 0.6 s 5, 6 low period of scl t low 1.3 s 5 high period of scl t high 0.6 s 5 repeated start condition setup time to rising scl t su:sta 0.6 s 5 data-out hold time from falling scl t hd:dat 0 0.9 s 5 data-in setup time to rising scl t su:dat 100 ns 5 rise time of sda and scl t r 20 + 0.1c b 1000 ns 5, 7 fall time of sda and scl t f 20 + 0.1c b 300 ns 5, 7 stop setup time to rising scl t su:sto 0.6 s 5 capacitive load for each bus line c b 400 pf input capacitance c i 5 pf notes: 1. all voltages are referenced to ground. 2. internal heating caused by o.s. loading will cause the ds75 to read approximately 0.5 c higher if o.s. is sinking the max rated current. 3. i dd specified with o.s. pin open. 4. i dd specified with v dd at 5.0v and sda, scl = 5.0v, 0 c to 70 c. 5. see timing diagram in figure 2. all timing is referenced to 0.9 x v dd and 0.1 x v dd . 6. after this period, the first clock pulse is generated. 7. for example, if c b = 300pf, then t r [min] = t f [min] = 50ns.
ds75 6 of 14 figure 2. timing diagram note: the ds75 does not delay the sda line internally with respect to scl for any length of time. operation?measuri ng temperature the ds75 measures temperature using a bandgap temp erature sensing architecture. an on-board delta- sigma analog-to-digital converter ( adc) converts the measured temperature to a digital value that is calibrated in degrees centigrade; for fahrenheit applications a lookup tabl e or conversion routine must be used. the ds75 is factory-calibrate d and requires no external component s to measure temperature. at power-up the ds75 immediately be gins measuring the temperature a nd converting the temperature to a digital value. the resolution of the digital output data is user-configurable to 9, 10, 11, or 12 bits, corresponding to temperat ure increments of 0.5 c, 0.25 c, 0.125 c, and 0.0625 c, respectively, with 9- bit default resolution at power-up. th e resolution is controlled via the r0 and r1 bits in the configuration register as explained in the configuration register section of this data sheet. note that the conversion time doubles for each additional bit of resolution. after each temperature measurement and analog-to-digi tal conversion, the ds75 stores the temperature as a 16-bit two?s complement number in the 2-byte te mperature register (see fi gure 3). the sign bit (s) indicates if the temperature is posi tive or negative: for positive numbers s = 0 and for negative numbers s = 1. the most recently converted di gital measurement can be read from the temperature register at any time. since temperature conversi ons are performed in the background, reading the temperature register does not affect the operation in progress. bits 3 through 0 of the temperatur e register are hardwired to 0. when the ds75 is configured for 12-bit resolution, the 12 msbs (bits 15 through 4) of the temp erature register will contain temperature data. for 11-bit resolution, the 11 msbs (bits 15 through 5) of the temperature regi ster will contain data, and bit 4 will read out as 0. likewise, for 10-bit resolution, th e 10 msbs (bits 15 through 6) will contain data, and for 9-bit the 9 msbs (bits 15 through 7) will contai n data, and all unused lsbs will contain 0s. table 3 gives examples of 12-bit reso lution digital output data and the corresponding temperatures.
ds75 7 of 14 figure 3. temperature, t h , and t l register format bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ms byte s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ls byte 2 -1 2 -2 2 -3 2 -4 0 0 0 0 table 3. 12-bit resolution te mperature/data relationship temperature ( c) digital output (binary) digital output (hex) +125 0111 1101 0000 0000 7d00h +25.0625 0001 1001 0001 0000 1910h +10.125 0000 1010 0010 0000 0a20h +0.5 0000 0000 1000 0000 0080h 0 0000 0000 0000 0000 0000h -0.5 1111 1111 1000 0000 ff80h -10.125 1111 0101 1110 0000 f5e0h -25.0625 1110 0110 1111 0000 e6f0h -55 1100 1001 0000 0000 c900h shutdown mode for power-sensitive applications , the ds75 offers a low-power s hutdown mode. the sd bit in the configuration register c ontrols shutdown mode. when sd is ch anged to 1, the conversion in progress will be completed and the result stored in the temper ature register after which the ds75 will go into a low-power standby state. the o.s. out put will be cleared if the thermost at is operating in interrupt mode and o.s will remain unchanged in comparator mode . the 2-wire interface remains operational in shutdown mode, and writing a 0 to the sd bit returns the ds75 to normal operation. operation?thermostat the ds75 thermostat has two operating modes, compar ator mode and interrupt mode, which activate and deactivate the open-drain thermostat output (o.s .) based on user-programmable trip-points (t os and t hyst ). the ds75 powers up with the thermostat in co mparator mode with active-low o.s. polarity and with the over-temperature trip-point (t os ) register set to 80 c and the hysteresis trip-point (t hyst ) register set to 75 c. if these power-up settings are compatible with the application, the ds75 can be used as a standalone thermostat (i.e., no 2?wire communica tion required). if interrupt mode operation, active- high o.s. polarity or different t os and t hyst values are desired, they must be programmed after power- up, so standalone opera tion is not possible. in both operating modes, the user can program the th ermostat fault tolerance, which sets how many consecutive temperature readings ( 1, 2, 4, or 6) must fall outside of the thermostat limits before the thermostat output is triggered. the fault tolerance is set by the f1 and f0 bits in the configuration and at power-up the fault tolerance is 1. the data format of the t os and t hyst registers is identical to that of the temperature register (see figure 3), i.e., a two-byte two?s complement representation of the trip-point temperature in degrees centigrade with bits 3 through 0 hardwired to 0. after every temperature conversion, the measured temperature is
ds75 8 of 14 compared to the values in the t os and t hyst registers, and then o.s. is u pdated based on the result of the comparison and the operating mode. the number of t os and t hyst bits used during the thermostat comparison is equal to the conversion resolution set by the r1 and r0 bits in th e configuration register. for example, it the resolution is 9 bits, only the 9 msbs of t os and t hyst will be used by the thermostat comparator. the active state of the o.s. output can be changed via the pol bit in the configuration register. the power-up default is active low. if the user does not wish to use the thermostat capabilities of the ds 75, the o.s. output should be left floating. note that if the th ermostat is not used, the t os and t hyst registers can be used for general storage of system data. comparator mode ? when the thermostat is in comparator mode, o.s. can be programmed to operate with any amount of hysteresis. the o.s. output b ecomes active when the measured temperature exceeds the t os value a consecutive number of times as defined by the f1 and f0 fault tolerance (ft) bits in the configuration register. o.s. then stays active until the first time the temperature falls below the value stored in t hyst . putting the device into shutdown mode doe s not clear o.s. in comparator mode. thermostat comparator mode operation w ith ft = 2 is illustrated in figure 4. interrupt mode ? in interrupt mode, the o.s. output first becomes active when the measured temperature exceeds the t os value a consecutive number of times equal to the ft value in the configuration register. once activat ed, o.s. can only be cleared by ei ther putting the ds75 into shutdown mode or by reading from any regist er (temperature, configuration, t os , or t hyst ) on the device. once o.s. has been deactivated, it will only be reactivat ed when the measured temperature falls below the t hyst value a consecutive number of times equal to the ft value. again, o.s can only be cleared by putting the device into shutdown mode or reading any register. thus, this interrupt/clear process is cyclical between t os and t hyst events (i.e, t os , clear, t hyst , clear, t os , clear, t hyst , clear, etc.). thermostat interrupt mode operation with ft = 2 is illustrated in figure 4. figure 4. o.s. output operation example in this example the ds75 is configured to have a fault tolerance of 2. o.s. output - comparator mode conversions inactive active temperature t os t hyst inactive active o.s. output - interrupt mode assumes a read has occurred
ds75 9 of 14 configuration register the configuration register allows the user to program various ds75 options such as conversion resolution, thermostat fault tolera nce, thermostat polarity, thermo stat operating mode, and shutdown mode. the configuration re gister is arranged as show n in figure 5 and detailed descriptions of each bit are provided in table 4. the user ha s read/write access to all bits in th e configuration register except the msb, which is a reserved read-only bit. the entire regi ster is volatile, and thus powers?up in its default state. figure 5. configuration register msb b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 lsb 0 r1 r0 f1 f0 pol tm sd table 4. configuration re gister bit descriptions bit name functional description 0 reserved power-up state = 0 the master can write to this bit, but it will always read out as a 0. r1 conversion resolution bit 1 power-up state = 0 sets conversion resolution (see table 5) r0 conversion resolution bit 0 power-up state = 0 sets conversion resolution (see table 5) f1 thermostat fault tolerance bit 1 power-up state = 0 sets the thermostat fault tolerance (see table 6). f0 thermostat fault tolerance bit 0 power-up state = 0 sets the thermostat fault tolerance (see table 6). pol thermostat output (o.s.) polarity power-up state = 0 pol = 0 ? o.s. is active low. pol = 1 ? o.s. is active high. tm thermostat operating mode power-up state = 0 tm = 0 ? comparator mode. tm = 1 ? interrupt mode. see the operation?thermostat section for a detailed description of these modes. sd shutdown power-up state = 0 sd = 0 ? active conversion and thermostat operation. sd = 1 ? shutdown mode. see the shutdown mode section for a detailed description of this mode. table 5. resoluti on configuration r1 r0 thermometer resolution max conversion time 0 0 9?bit 150 ms 0 1 10?bit 300 ms 1 0 11?bit 600 ms 1 1 12?bit 1200 ms
ds75 10 of 14 table 6. fault tolerance configuration f1 f0 consecutive out-of-limits conversions to trigger o.s. 0 0 1 0 1 2 1 0 4 1 1 6 register pointer the four ds75 registers each have a unique two-bit po inter designation, which is defined in table 7. when reading from or writing to the ds75, the user must ?point? the ds75 to the register that is to be accessed. when reading from the ds75, once the pointer is set, it will remain pointed at the same register until it is changed. for example, if the user desi res to perform consecutive reads from the temperature register, then the pointer only has to be set to the temperature register one time, after which all reads will automatically be from the temperature register until the pointer value is changed. on the other hand, when writing to the ds75, the pointer value must be re freshed each time a write is performed even if the same register is being written to twice in a row. at power-up, the default pointer value is the temperature register so the temperature register can be read immediately without resetting the pointer. changes to the pointer setting are accomplished as described in the 2-wire serial data bus section of this datasheet. table 7. pointer definition register p1 p0 temperature 0 0 configuration 0 1 t hyst 1 0 t os 1 1 2-wire serial data bus the ds75 communicates over a standard bi-directional 2-wi re serial data bus that consists of a serial clock (scl) signal and serial data (sda) signal. the ds75 interfaces to the bus via the scl input pin and open-drain sda i/o pin. all co mmunication is msb first. the following terminology is used to describe 2-wire communication: master device: microprocessor/microcontroller that contro ls the slave devices on the bus. the master device generates the scl signal and start and stop conditions. slave: all devices on the bus other than the mast er. the ds75 always functions as a slave. bus idle or not busy: both sda and scl remain high. sda is held high by a pullup resistor when the bus is idle, and scl must either be forced high by the master (if the scl output is push-pull) or pulled high by a pullup resistor (if th e scl output is open-drain). transmitter: a device (master or slave) that is sending data on the bus. receiver: a device (master or slave) that is receiving data from the bus.
ds75 11 of 14 start condition: signal generated by the master to indica te the beginning of a data transfer on the bus. the master generates a start condition by pulli ng sda from high to low while scl is high (see figure 6). a ?repeated? start is sometimes used at th e end of a data transfer (instead of a stop) to indicate that the master w ill perform another operation. stop condition: signal generated by the master to indicate the end of a data tran sfer on the bus. the master generates a stop condition by transitioning sda from low to high while scl is high (see figure 6). after the stop is issued, the master releases the bus to its idle state. acknowledge (ack): when a device (either master or slave) is acting as a rece iver, it must generate an acknowledge (ack) on the sda line after receiving every byte of data. the receiving device performs an ack by pulling the sda line low for an entire scl period (see figure 6). during the ack clock cycle, the transmitting device must release sda. a varia tion on the ack signal is the ?not acknowledge? (nack). when the master device is acting as a receiver, it uses a nack instead of an ack after the last data byte to indicate that it is finished receiving data. the master indicates a nack by leaving the sda line high during the ack clock cycle. slave address: every slave device on the bus has a unique 7-bit address that allows the master to access that device. the ds75?s 7-b it bus address is 1 0 0 1 a 2 a 1 a 0 , where a 2 , a 1 and a 0 are user-selectable via the corresponding input pins. the three address pins allow up to eight DS75S to be multi-dropped on the same bus. address byte: the control byte is transmitted by the master and consists of the 7-bit slave address plus a read/write (r/ w ) bit (see figure 7). if the master is going to read data from the slave device then r/ w = 1, and if the master is going to writ e data to the slave device then r/ w = 0. pointer byte: the pointer byte is used by th e master to tell the ds75 which register is going to be accessed during communication. the six lsbs of the point er byte (see figure 8) are always 0 and the two lsbs correspond to the desired re gister as shown in table 7. figure 6. start, st op, and ack signals figure 7. address byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 0 0 1 a 2 a 1 a 0 r/ w figure 8. pointer byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scl sda start condition stop condition ? ? ack (or nack) from receiver
ds75 12 of 14 0 0 0 0 0 0 p1 p0 general 2-wire information ? all data is transmitted msb first over the 2-wire bus. ? one bit of data is transmitted on the 2-wire bus each scl period. ? a pullup resistor is required on the sda line and, wh en the bus is idle, both sda and scl must remain in a logic-high state. ? all bus communication must be initiated with a start condition and terminated with a stop condition. during a start or stop is the only time sd a is allowed to change states while scl is high. at all other times, changes on the sda line can only occur when scl is low: sda must remain stable when scl is high. ? after every 8-bit (1-byte) transf er, the receiving device must answ er with an ack (or nack), which takes one scl period. therefore, nine clocks are required for every on e-byte data transfer. writing to the ds75 ? to write to the ds75, the master must generate a start followed by an address byte containing the ds75 bu s address. the value of the r/ w bit must be a 0, which indicates that a write is about to take place. the ds75 will respond with an ack after receiving the address byte. this must be followed by a pointer byte from the master, which tells the ds75 which register is being written to. the ds75 will again respond with an ack after re ceiving the pointer byte. following this ack the master device must immediately begin transmitting data to the ds75. when writing to the configuration register, the master must send one byte of data (see figure 9a ), and when writing to the t os or t hyst registers the master must send two bytes of data (s ee figure 9b). after receiving each data byte, the ds75 will respond with an ack, and the transaction is finished with a stop from the master. reading from the ds75 ? when reading from the ds75, if the pointer was already pointed to the desired register during a previous transaction, the read can be perfor med immediately without changing the pointer setting. in this cas e the master sends a start followe d by an address byte containing the ds75 bus address. the r/w bit must be a 1, which te lls the ds75 that a read is being performed. after the ds75 sends an ack in response to the address byte, the ds75 will begin transmitting the requested data on the next clock cycle. when reading from the configuration register, the ds75 will transmit one byte of data, after which the master must respond with a nack followed by a stop (see figure 9c). for two-byte reads (i.e., from the temperature, t os or t hyst register), the ds75 will transmit two bytes of data, and the master must respond to the first data byte with an ack and to the second byte with a nack followed by a stop (see figure 9d). if only the most significant byte of data is needed, the master can issue a nack followed by a stop after reading the first data byte in which case the transaction will be the same as for a read from the configuration register. if the pointer is not already pointing to the desired re gister, the pointer must fi rst be updated as shown in figure 9e, which shows a pointer update followe d by a single-byte read. the value of the r/ w bit in the initial address byte is a 0 (?write?) since the master is going to write a pointer byte to the ds75. after the ds75 to the address byte with an ack, the master sends a pointer byte that corresponds to the desired register. the master must then perform a repeated start followed by a standa rd one or two byte read sequence (with r/ w =1) as described in the previous paragraph.
ds75 13 of 14 figure 9. 2-wire interface timing (ds75) (ds75) a d2 d6 d5 d4 d3 d1 d0 a0 w a a1 0 0 0 0 0 001ad7 a2 a) write to the configuration register s1 1 00 address byte start scl sda ack pointer byte p data byte (from master) stop ack ack (ds75) b) write to the t os or t hyst register a2 a1 a0 scl sda s 1 1 0 0w a address byte start ack (ds75) a 0 0000 0 p1 p0 pointer byte ack (ds75) d4 d6 d5 d3 d2 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 a d1 p ls data byte (from master) a ms data byte (from master) stop ack (ds75) ack (ds75) s c) read from the configuration register (current pointer location) scl sda start n d6 d5 d4 d3 d2 d1 d0 p d7 1 1 00 a2 a1 a0 ra data byte (from ds75) stop nack (master) address byte ack (ds75) s d) read 2-bytes from the temperature, t os or t hyst register (current pointer location) scl sda start a d6 d5 d4 d3 d2 d1 d0 d7 1 1 00 a2 a1 a0 ra ms data byte (from ds75) ack (master) address byte ack (ds75) n d6 d5 d4 d3 d2 d1 d0 p d7 ls data byte (from ds75) stop nack (master) n a0 s1 1 00 a2 a1 a0 w 000 a 0 0d6d5 d4 d3 d2 d1 d0 p d7 s1 1 00 a2 a1 a0 ra e) read single byte (new pointer location) ack (ds75) repeat start scl sda address byte start pointer byte data byte (from ds75) stop nack (master) address byte ack (ds75) ack (ds75) p1 p0
ds75 14 of 14 revision history revision date description pages changed 022108 deleted all references to flip-chip package. added registered trademark symbol to max. 1, 2

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